Alif Semiconductor /AE302F80F5582AE_CM55_HE_View /ETH /ETH_MAC_TIMESTAMP_STATUS

Timestamp Seconds Overflow When this bit is set, it indicates that the ETH_MAC_SYSTEM_TIME_SECONDS[TSS] value has overflowed beyond 0xFFFF_FFFF. Access restriction applies. Clears on read (or this bit is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event.

0 (Val_0x0): Timestamp seconds overflow status not detected

1 (Val_0x1): Timestamp seconds overflow status detected

Timestamp Target Time Reached When set, this bit indicates that the value of system time is greater than or equal to the value specified in the ETH_MAC_PPS0_TARGET_TIME_SECONDS and ETH_MAC_PPS0_TARGET_TIME_NANOSECONDS registers. Access restriction applies. Clears on read (or this bit is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event.

0 (Val_0x0): Timestamp target time reached status not detected

1 (Val_0x1): Timestamp target time reached status detected

Timestamp Target Time Error This bit is set when the latest target time programmed in the ETH_MAC_PPS0_TARGET_TIME_SECONDS and ETH_MAC_PPS0_TARGET_TIME_NANOSECONDS registers elapses. Access restriction applies. Clears on read (or this bit is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event.

0 (Val_0x0): Timestamp target time error status not detected

1 (Val_0x1): Timestamp target time error status detected

Tx Timestamp Status Interrupt Status When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the ETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and ETH_MAC_TX_TIMESTAMP_STATUS_SECONDS registers. This bit is cleared when the ETH_MAC_TX_TIMESTAMP_STATUS_SECONDS register is read (or write to ETH_MAC_TX_TIMESTAMP_STATUS_SECONDS register when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set).

0 (Val_0x0): Tx timestamp status interrupt status not detected

1 (Val_0x1): Tx timestamp status interrupt status detected